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isplsi 2096e in-system programmable superfast? high density pld 2096e_04 1 features ? superfast high density in-system programmable logic ? 4000 pld gates ? 96 i/o pins, six dedicated inputs ? 96 registers ? high speed global interconnect ? wide input gating for fast counters, state machines, address decoders, etc. ? small logic block size for random logic ? 100% functional/jedec upward compatible with isplsi 2096 devices ? high performance e 2 cmos ? technology ? f max = 180 mhz maximum operating frequency ? t pd = 5.0 ns propagation delay ? ttl compatible inputs and outputs ? 5v programmable logic core ? ispjtag? in-system programmable via ieee 1149.1 (jtag) test access port ? user-selectable 3.3v or 5v i/o supports mixed- voltage systems ? pci compatible outputs ? open-drain output option ? electrically erasable and reprogrammable ? non-volatile ? unused product term shutdown saves power ? isplsi offers the following added features ? increased manufacturing yields, reduced time-to- market and improved product quality ? reprogram soldered devices for faster prototyping ? offers the ease of use and fast system speed of plds with the density and flexibility of field programmable gate arrays ? complete programmable device can combine glue logic and structured designs ? enhanced pin locking capability ? three dedicated clock input pins ? synchronous and asynchronous clocks ? programmable output slew rate control to minimize switching noise ? flexible pin placement ? optimized global routing pool provides global interconnectivity functional block diagram copyright ? 2002 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respec tive holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. t el. (503) 268-8000; 1-800-lattice; fax (503) 268-8556; http://www.latticesemi.com january 2002 description the isplsi 2096e is a high density programmable logic device. the device contains 96 registers, 96 universal i/o pins, six dedicated input pins, three dedicated clock input pins, two dedicated global oe input pins and a global routing pool (grp). the grp provides complete interconnectivity between all of these elements. the isplsi 2096e features 5v in-system programmability and in-system diagnostic capabilities. the isplsi 2096e offers non-volatile reprogrammability of all logic, as well as the interconnect to provide truly reconfigurable sys- tems. the basic unit of logic on the isplsi 2096e device is the generic logic block (glb). the glbs are labeled a0, a1 .. c7 (see figure 1). there are a total of 24 glbs in the isplsi 2096e device. each glb is made up of four macrocells. each glb has 18 inputs, a programmable and/or/exclusive or array, and four outputs which can be configured to be either combinatorial or registered.inputs to the glb come from the grp and dedicated inputs. all of the glb outputs are brought back into the grp so that they can be connected to the inputs of any glb on the device. the device also has 96 i/o cells, each of which is directly connected to an i/o pin. each i/o cell can be individually programmed to be a combinatorial input, output or bi- directional i/o pin with 3-state control. the signal levels are ttl compatible voltages and the output drivers can source 4 ma or sink 8 ma. each output can be pro- grammed independently for fast or slow output slew rate to minimize overall output switching noise. by connecting global routing pool (grp) output routing pool (orp) output routing pool (orp) 0919/2096e c7 c4 c5 c6 a4 a7 a6 a5 glb logic array dq dq dq dq output routing pool (orp) output routing pool (orp) c3 c0 c1 c2 b0 b3 b2 b1 output routing pool (orp) output routing pool (orp) b7 b6 b4 b5 a0 a1 a3 a2
specifications isplsi 2096e 2 functional block diagram figure 1. isplsi 2096e functional block diagram the vccio pins to a common 5v or 3.3v power supply, i/o output levels can be matched to 5v or 3.3v compat- ible voltages. when connected to a 5v supply, the i/o pins provide pci-compatible output drive. eight glbs, 32 i/o cells, two dedicated inputs and two orps are connected together to make a megablock (see figure 1). the outputs of the eight glbs are connected to a set of 32 universal i/o cells by the two orps. each isplsi 2096e device contains three megablocks. the grp has as its inputs, the outputs from all of the glbs and all of the inputs from the bi-directional i/o cells. all of these signals are made available to the inputs of the glbs. delays through the grp have been equalized to minimize timing skew. clocks in the isplsi 2096e device are selected using the dedicated clock pins. three dedicated clock pins (y0, y1, y2) or an asynchronous clock can be selected on a glb basis. the asynchronous or product term clock can be generated in any glb for its own clock. programmable open-drain outputs in addition to the standard output configuration, the outputs of the isplsi 2096e are individually program- mable, either as a standard totem-pole output or an open-drain output. the totem-pole output drives the specified voh and vol levels, whereas the open-drain output drives only the specified vol. the voh level on the open-drain output depends on the external loading and pull-up. this output configuration is controlled by a pro- grammable fuse. the default configuration when the device is in bulk erased state is totem-pole configuration. the open-drain/totem-pole option is selectable through the lattice software tools. a0 a3 a1 a2 b7 b4 b6 b5 output routing pool (orp) output routing pool (orp) input bus input bus global routing pool (grp) clk 0 clk 1 clk 2 i/o 95 i/o 94 i/o 93 i/o 92 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 i/o 32 i/o 33 i/o 34 i/o 35 in 2 tck/in 3 i/o 36 i/o 37 i/o 38 i/o 39 i/o 40 i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 i/o 46 i/o 47 y0 y1 y2 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 63 i/o 62 i/o 61 i/o 60 i/o 59 i/o 58 i/o 57 i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 i/o 49 i/o 48 tdi/in 0 tms/in 1 tdo reset bscan goe 1 goe 0 i/o 91 i/o 90 i/o 89 i/o 88 i/o 87 i/o 86 i/o 85 i/o 84 i/o 83 i/o 82 i/o 81 i/o 80 input bus 0917/2096e megablock c7 c6 c5 c4 a4 a5 a6 a7 output routing pool (orp) output routing pool (orp) input bus input bus b0 b1 b2 b3 output routing pool (orp) c3 c2 c1 c0 output routing pool (orp) input bus i/o 79 i/o 78 i/o 77 i/o 76 i/o 75 i/o 74 i/o 73 i/o 72 i/o 71 i/o 70 i/o 69 i/o 68 i/o 67 i/o 66 i/o 65 i/o 64 in 5 in 4 generic logic blocks (glbs)
specifications isplsi 2096e 3 absolute maximum ratings 1 supply voltage v cc .................................. -0.5 to +7.0v input voltage applied ........................ -2.5 to v cc +1.0v off-state output voltage applied ..... -2.5 to v cc +1.0v storage temperature ................................ -65 to 150 c case temp. with power applied .............. -55 to 125 c max. junction temp. (t j ) with power applied ... 150 c 1. stresses above those listed under the ?absolute maximum ratings? may cause permanent damage to the device. functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). dc recommended operating condition capacitance (t a =25 c, f=1.0 mhz) erase/reprogram specification t a = 0 c to +70 c symbol table 2-0005/2096e v cc v ih v il parameter supply voltage: logic core, input buffers input high voltage input low voltage min. max. units 4.75 2.0 0 5.25 v cc +1 0.8 v v ccio supply voltage: output drivers 4.75 5.25 v 3.3v 5v 3.0 3.6 v v v c symbol table 2-0006/2096e c parameter i/o capacitance units test conditions 1 2 dedicated input capacitance pf pf v = 5.0v, v = 2.0v v = 5.0v, v = 2.0v cc cc i/o in c clock capacitance 8 typ 8 10 3 pf v = 5.0v, v = 2.0v cc y table 2-0008/2096e parameter minimum maximum units erase/reprogram cycles 10,000 ? cycles
specifications isplsi 2096e 4 switching test conditions figure 2. test load + 5v r 1 r 2 c l * device output test point * c l includes test fixture and probe capacitance. 0213a test condition r1 r2 cl a 470 ? 390 ? 35pf b 390 ? 35pf 470 ? 390 ? 35pf active high active low c 470 ? 390 ? 5pf 390 ? 5pf active low to z at v +0.5v ol active high to z at v -0.5v oh table 2 - 0004a/2000 output load conditions (see figure 2) input pulse levels table 2-0003/2128e input rise and fall time 10% to 90% input timing reference levels output timing reference levels output load gnd to 3.0v 1.5v 1.5v see figure 2 3-state levels are measured 0.5v from steady-state active level. 1.5 ns v ol symbol 1. one output at a time for a maximum duration of one second. v out = 0.5v was selected to avoid test problems by tester ground degradation. characterized but not 100% tested. 2. meaured using six 16-bit counters. 3. typical values are at v cc = 5v and t a = 25 c. 4. unused inputs held at 0.0v. 5. maximum i cc varies widely with specific device configuration and operating frequency. refer to the power consumption section of this data sheet and the thermal management section of the lattice semiconductor data book or cd-rom to estimate maximum i cc . table 2-0007/2096e v oh i ih i il parameter i il-pu i os 1 i cc 3,4 output low voltage output high voltage input or i/o low leakage current operating power supply current i ol = 8 ma i oh = -4 ma 0v v in v il (max.) v il = 0.0v, v ih = 3.0v condition min. typ. 3 max. units ? 2.4 ? ? ? ? ? ? ? ? 0.4 ? 10 -10 10 v v a input or i/o high leakage current v ccio v in 5.25v (v ccio - 0.2)v v in v ccio a a i/o active pull-up current 0v v in 2.0v -10 ? -250 a output short circuit current v ccio = 5.0v or 3.3v, v out = 0.5v ? ? -240 ma ? 130 ma ? f toggle = 1 mhz dc electrical characteristics over recommended operating conditions
specifications isplsi 2096e 5 t pd1 units -180 min. test cond. 1. unless noted otherwise, all parameters use a grp load of four glbs, 20 ptxor path, orp and y0 clock. 2. refer to timing model in this data sheet for further details. 3. standard 16-bit counter using grp feedback. 4. reference switching test conditions section. table 2-0030a/2096e 1 1 tsu2 + tco1 ( ) -135 min. max. max. description # 2 4 parameter a1 data prop delay, 4pt bypass, orp bypass ? 5.0 ? 7.5 ns t pd2 a2 data prop delay ? ? ns f max a3 clk freq with internal feedback 3 180 ? 135 ? mhz f max (ext.) ? 4 clk freq with external feedback ? ? mhz f max (tog.) ? 5 clk frequency, max. toggle ? ? mhz t su1 ? 6 glb reg setup time before clk, 4 pt bypass ? ? ns t co1 a7 glb reg clk to output delay, orp bypass ? ? ns t h1 ? 8 glb reg hold time after clk, 4 pt bypass 0.0 ? ns t su2 ? 9 glb reg setup time before clk 5.0 ? ns t co2 ? 10 glb reg clk to output delay ? ? ns t h2 ? 11 glb reg hold time after clk 0.0 ? ns t r1 a1 2 external reset pin to output delay ? ? ns t rw1 ? 13 external reset pulse duration 4.0 ? ns t ptoeen b1 4 input to output enable ? ? ns t ptoedis c1 5 input to output disable ? ? ns t goeen b1 6 global oe output enable ? ? ns t goedis c1 7 global oe output disable ? ? ns t wh ? 18 external synch clk pulse duration, high 2.5 ? ? ns t wl ? 19 external synch clk pulse duration, low 2.5 ? ? ns 125 200 4.0 3.0 ? ? 3.5 ? 7.0 ? 10.0 10.0 5.0 5.0 7.5 100 143 5.0 0.0 6.0 0.0 5.0 3.5 3.5 10.0 4.0 4.5 10.0 12.0 12.0 7.0 7.0 -100 min. max. ? 10.0 ? 100 ? ? ? ? ? 0.0 8.0 ? 0.0 ? 6.5 ? ? ? ? 5.0 ? 5.0 ? 77 100 6.5 5.0 ? ? 6.0 ? 13.5 ? 15.0 15.0 9.0 9.0 13.0 external timing parameters over recommended operating conditions
specifications isplsi 2096e 6 internal timing parameters 1 over recommended operating conditions t io 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. 3. the xor adjacent path can only be used by hard macros. table 2-0036a/2096e inputs units -135 min. max. description # 2 parameter 20 input buffer delay ? 0.5 ns t din 21 dedicated input delay ? 1.7 ns t grp 22 grp delay ? 1.2 ns glb t 1ptxor 25 1 product term/xor path delay ? 5.2 ns t 20ptxor 26 20 product term/xor path delay ? 5.2 ns t xoradj 27 xor adjacent path delay ? 5.2 ns t gbp 28 glb register bypass delay ? 0.5 ns t gsu 29 glb register setup time before clock 0.7 ? ns t gh 30 glb register hold time after clock 4.3 ? ns t gco 31 glb register clock to output delay ? 0.3 ns 3 t gro 32 glb register reset to output delay ? 1.1 ns t ptre 33 glb product term reset to register delay ? 6.0 ns t ptoe 34 glb product term output enable to i/o cell delay ? 6.9 ns t ptck 35 glb product term clock delay 2.5 5.5 ns orp t ob 38 output buffer delay ? 1.6 ns t sl 39 output slew limited delay adder ? 1.5 ns grp t 4ptbpc 23 4 product term bypass path delay (combinatorial) ? 3.7 ns t 4ptbpr 24 4 product term bypass path delay (registered) ? 4.2 ns t orp 36 orp delay ? 1.0 ns t orpbp 37 orp bypass delay ? 0.5 ns outputs t oen 40 i/o cell oe to output enabled ? 3.4 ns t odis 41 i/o cell oe to output disabled ? 3.4 ns t goe 42 global output enable ? 3.6 ns t gy0 43 clock delay, y0 to global glb clock line (ref. clock) 1.6 1.6 ns t gy1/2 44 clock delay, y1 or y2 to global glb clock line 1.8 1.8 ns clocks t gr 45 global reset to glb ? 6.3 ns global reset -180 min. max. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0.5 1.1 0.6 ? ? 3.9 3.9 3.9 0.0 1.9 2.9 0.7 3.3 0.3 0.6 4.8 5.9 1.0 4.0 ? ? 0.9 0.4 1.6 1.5 ? ? 3.0 3.0 ? 2.0 0.7 0.9 0.7 0.9 ? 4.4 -100 min. max. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0.5 2.2 1.7 ? ? 6.8 7.3 8.0 0.5 5.8 5.8 1.2 4.0 0.3 1.3 6.1 8.6 4.1 7.1 ? ? 1.4 0.4 1.6 1.0 ? ? 4.2 4.2 ? 4.8 2.7 2.7 2.7 2.7 ? 9.2
specifications isplsi 2096e 7 isplsi 2096e timing model note: calculations are based upon timing specifications for the isplsi 2096e-180l. derivations of t su, t h and t co from the product term clock = = = = t su logic + reg su - clock (min) ( t io + t grp + t 20ptxor) + ( t gsu) - ( t io + t grp + t ptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #35) (0.5 + 0.6 + 3.9) + (0.7) - (0.5 + 0.6 + 1.0) = = = = t h clock (max) + reg h - logic ( t io + t grp + t ptck(max)) + ( t gh) - ( t io + t grp + t 20ptxor) (#20 + #22 + #35) + (#30) - (#20 + #22 + #26) (0.5 + 0.6 + 4.0) + (3.3) - (0.5 + 0.6 + 3.9) = = = = t co clock (max) + reg co + output ( t io + t grp + t ptck(max)) + ( t gco) + ( t orp + t ob) (#20 + #22 + #35) + (#31) + (#36 + #38) (0.5 + 0.6 + 4.0) + (0.3) + (0.9 + 1.6) table 2-0042/2096e 3.6 3.4 7.9 glb reg delay i/o pin (output) orp delay feedback reg 4 pt bypass 20 pt xor delays control pts i/o pin (input) y0,1,2 grp glb reg bypass orp bypass dq rst re oe ck i/o delay i/o cell orp glb grp i/o cell #24 #25 - 27 #33 - 35 #43, 44 #36 reset ded. in #21 #20 #28 #29 - 32 goe0, 1 #42 #40, 41 0491/2096e #22 comb 4 pt bypass #23 #37 #45 #38, #39
specifications isplsi 2096e 8 power consumption power consumption in the isplsi 2096e device depends on two primary factors: the speed at which the device is operating and the number of product terms used. figure 3 shows the relationship between power and operating speed. figure 3. typical device power consumption vs fmax 0127/2096e i cc can be estimated for the isplsi 2096e using the following equation: i cc = 5.5 + (# of pts * 0.67) + (# of nets * max freq * 0.0047) where: # of pts = number of product terms used in design # of nets = number of signals used in device max freq = highest clock frequency to the device (in mhz) the i cc estimate is based on typical conditions (v cc = 5.0v, room temperature) and an assumption of two glb loads on average exists. these values are for estimates only. since the value of i cc is sensitive to operating conditions and the program in the device, the actual i cc should be verified. 125 175 225 250 275 300 325 350 020406 080 100 120 140 160 180 f max (mhz) i cc (ma) notes: configuration of six 16-bit counters typical current at 5v, 25 c 200 150 isplsi 2096e
specifications isplsi 2096e 9 pin description input - this pin performs two functions. when bscan is logic low, it functions as a pin to control the operation of the isp state machine. when bscan is high, it functions as a dedicated input pin. 1. pins have dual function capability. input/output pins - these are the general purpose i/o pins used by the logic array. name table 2-0002/2096e pqfp & tqfp pin numbers description 21, 27, 34, 40, 52, 58, 66, 72, 85, 91, 98, 104, 117, 123, 2, 8, 18 46 78 15 19 50 20 22, 28, 35, 41, 53, 59, 67, 73, 86, 92, 99, 105, 118, 124, 3, 9, 64, 114 23, 29, 36, 42, 54, 60, 68, 74, 87, 93, 100, 106, 119, 125, 4, 10, 110 i/o 0 - i/o 5 i/o 6 - i/o 11 i/o 12 - i/o 17 i/o 18 - i/o 23 i/o 24 - i/o 29 i/o 30 - i/o 35 i/o 36 - i/o 41 i/o 42 - i/o 47 i/o 48 - i/o 53 i/o 54 - i/o 59 i/o 60 - i/o 65 i/o 66 - i/o 71 i/o 72 - i/o 77 i/o 78 - i/o 83 i/o 84 - i/o 89 i/o 90 - i/o 95 24, 30, 37, 43, 55, 61, 69, 75, 88, 94, 101, 107, 120, 126, 5, 11, 25, 31, 38, 44, 56, 62, 70, 76, 89, 95, 102, 108, 121, 127, 6, 12, 26 32 39 45 57 63 71 77 90 96 103 109 122 128 7 13 1, 97, 17, 112, 33, 115, 49, 116 16, 48, 82, 113 65, 81, global output enables input pins. goe 0, goe 1 gnd v cc vcc ground (gnd) input - this pin performs two functions. when bscan is logic low, it functions as an input pin to load programming data into the device. tdi/in0 also is used as one of the two control pins for the isp state machine. when bscan is high, it functions as a dedicated input pin. dedicated clock input. this clock input is connected to one of the clock inputs of all the glbs on the device. active low (0) reset pin which resets all of the glb and i/o registers in the device. input - dedicated in-system programming enable input pin. this pin is brought low to enable the programming mode. the tms, tdi, tdo and tck options become active. reset y0, y1, y2 tdi/in 0 1 bscan tms/in 1 1 51, 84, 80 83, dedicated input pins to the device. in 2, in 4, in 5 output - when bscan is logic low, it functions as an output pin to read serial shift register data. tdo 1 input - this pin performs two functions. when bscan is logic low, it functions as a clock pin for the serial shift register. when bscan is high, it functions as a dedicated input pin. tck/in 3 1 14, 47, 79, 111 supply voltage for output drivers, 5v or 3.3v. all vccio pins must be connected to the same voltage level vccio
specifications isplsi 2096e 10 pin configuration isplsi 2096e 128-pin pqfp and tqfp pinout diagram i/o 84 i/o 85 i/o 86 i/o 87 i/o 88 i/o 89 i/o 90 i/o 91 i/o 92 i/o 93 i/o 94 i/o 95 vccio y0 vcc gnd bscan reset i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 gnd i/o 58 i/o 57 i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 i/o 49 i/o 48 in 4 y1 vcc gnd y2 tck/in 3 1 i/o 47 i/o 46 i/o 45 i/o 44 i/o 43 i/o 42 i/o 41 i/o 40 i/o 39 i/o 38 i/o 37 i/o 36 i/o 83 i/o 82 i/o 81 i/o 80 i/o 79 i/o 78 i/o 77 i/o 76 i/o 75 i/o 74 i/o 73 i/o 72 gnd gnd vcc vccio in 5 i/o 71 i/o 70 i/o 69 i/o 68 i/o 67 i/o 66 i/o 65 i/o 64 i/o 63 i/o 62 i/o 61 i/o 60 gnd i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 1 tms/in 1 vcc gnd tdo in 2 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 i/o 32 i/o 33 i/o 34 i/o 35 isplsi 2096e top view i/o 10 1 tdi/in 0 i/o 59 gnd vccio gnd gnd vccio 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 128 127 126 125 124 123 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 64 96 122 goe 0 goe 1 1. pins have dual function capability. 0124/2096e
specifications isplsi 2096e 11 part number description isplsi 2096e ordering information table 2-0041/2096e family f max (mhz) 180 135 ordering number package 128-pin tqfp 128-pin tqfp t pd (ns) 5.0 7.5 isplsi isplsi 2096e-180lt128 180 128-pin pqfp 5.0 isplsi 2096e-180lq128 isplsi 2096e-135lt128 135 128-pin pqfp 7.5 isplsi 2096e-135lq128 100 128-pin tqfp 10.0 isplsi 2096e-100lt128 100 128-pin pqfp 10.0 isplsi 2096e-100lq128 device number isplsi 2096e xxx x xxxx grade blank = commercial x speed 180 = 180 mhz f max 135 = 135 mhz f max 100 = 100 mhz f max power l = low package t128 = tqfp q128 = pqfp ? device family 0212/2096e

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